1. Field of the Invention
The present invention relates to semiconductor manufacturing, and more particularly to a method of fabricating a cylindrical capacitor storage node having HSG silicon on inner walls of the cylindrical storage node.
2. Description of the Related Art
Recent advances in the scaling-down of integrated circuit devices have led to smaller wafer areas. High-density DRAM (dynamic random access memory) devices, for example, leave little room for a storage node of a memory cell. Yet even as the footprint (area of a silicon wafer allotted for individual memory cells) shrinks, the storage node must maintain a certain minimum charge storage capacity (cell capacitance), determined by design and operational parameters, to ensure reliable operation of the memory cell. Cell capacitance must be maintained at least 25 fF for preventing and limiting soft-error rate caused by alpha-particle interference and data-error rate caused by noise. It is thus increasingly important in the semiconductor integrated circuits industry of high-level integration that capacitors achieve a high charge storage per unit area of the wafer. For this reason, capacitor structures have become more and more complicated, from planar cell to trench cell or stack cell designs, and the CUB (capacitor under bit line) structure is being replaced by COB (capacitor over bit line) structure.
As is well known, cell capacitance may be represented by the following equation: C (capacitance)=xcex5xc3x97A/d, where xcex5 is the dielectric constant of the capacitor dielectric, A is the electrode area and d represents the spacing between electrodes (thickness of the dielectric film). Accordingly, several techniques have been recently developed to increase the overall capacitance of the cell capacitor without significantly affecting the wafer area occupied by the cell. A first way is to use new materials having high dielectric constant. A second way is to form very thin dielectric films. A third way is to increase the effective surface area of the capacitor electrodes. However, application of high dielectric constant material as a dielectric film is still under study, and also has some problems associated with reliability. In addition, it is very difficult to form such thin dielectric films without reliability problems.
Accordingly, the third way is generally used to increase capacitance of the cell capacitor. To this end, three-dimensional capacitors such as stacked-type, cylindrical-type, trench-type, fin-type or the like, have been suggested to increase cell capacitance in a given cell area. Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably suitable for use as a three-dimensional capacitor, and is more particularly suitable for an integrated memory cell. Furthermore, new technologies have recently been developed for increasing the effective surface area by modifying the surface morphology of the polysilicon storage electrode itself, by engraving or controlling the nucleation and growth conditions of polysilicon. A hemispherical-grain (HSG) polysilicon layer can be deposited over a storage node to increase surface area and capacitance. However, as design rules have been scaled down to sub-quarter micron level, the possibility of an electrical bridge between adjacent storage nodes significantly increases when HSG silicon is grown on the outer surface of the cylindrical storage node.
To solve this problem associated with electrical bridges, a method for forming HSG silicon only on an inner surface of the cylindrical storage node has been suggested. Such method includes the step of forming HSG silicon on an inner surface of the cylindrical storage node, and then removing a sacrificial oxide layer to expose an outer surface of the storage node, by using wet chemicals. However, this method also has the problem associated with electrical bridges between adjacent storage nodes. In this case, the HSG silicon dislodges from the inner surface of the storage node during the step of removing the sacrificial oxide layer by wet etching, thereby causing an electrical bridge.
U.S. Pat. No. 5,892,702, the disclosure of which is incorporated herein by reference, discloses a method for fabricating a cylindrical capacitor having HSG on an inner surface of a storage node. FIGS. 1A to 1J are cross-sectional views of a semiconductor substrate 10, at selected stages of a cylindrical capacitor fabrication process in U.S. Pat. No. 5,892,702. Referring to FIG. 1A, an opening 49 is formed in a sacrificial oxide layer 48. Thin second amorphous silicon layer 50 is formed in the opening 49 as shown in FIG. 1B. Resist layer 51 is formed to fill the opening 49 as shown in FIG. 1C. A planarization process is carried out to separate the device by unit cell, down to the sacrificial oxide layer 48, as shown in FIG. 1D. Next, as shown in FIGS. 1E and 1F, the sacrificial oxide layer 48 and the underlying first amorphous silicon layer 47a are respectively removed to form space 260 having amorphous silicon sidewall 28. The space 260 is filled with a spin-on-glass layer 52 as shown in FIG. 1G. Next, the remainder of the resist layer 51 in the opening 49 is selectively removed, thereby forming a cylindrical storage node 26 electrically isolated by the spin-on-glass layer 52 from adjacent nodes 261 and 262, as shown in FIG. 1H. HSG silicon 41 is formed on inner surfaces of the storage node (i.e., the second amorphous silicon 50) as shown in FIG. 11. Thereafter, the spin-on-glass layer 52 is removed to expose outer surfaces of the storage node as shown in FIG. 1J.
However, when the spin-on-glass layer 52 is removed in this fabrication process as described with respect to FIG. 1J, HSG silicon 41 formed on inner surfaces of the storage node can be dislodged therefrom, to cause electrical bridges between adjacent storage nodes. Accordingly, there is a strong need for a method of fabricating a capacitor storage node with high cell capacitance, but without electrical bridges between adjacent storage nodes.
The present invention is therefore directed to a method of fabricating a cylindrical capacitor storage node having HSG silicon on inner walls thereof, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art. More particularly, the present invention is directed toward providing a method of fabricating a capacitor storage node having HSG silicon only on inner walls thereof, without electrical bridges between adjacent storage nodes.
It is a feature of the present invention that HSG silicon is formed only on inner walls of the storage node. It is another feature of the present invention that HSG silicon is formed after a sacrificial oxide layer is removed. It is still another feature of the present invention that the storage node is made of a double layer-structure, one layer defining the inner wall of the storage node and the other defining an outer wall of the storage node, where the other layer defining the outer wall of the storage node is made of a conductive layer that suppresses the growth of HSG silicon thereon. It is still another feature of the present invention that a cylindrical opening for a storage node can be formed with a sufficient photolithography process margin.
To achieve these objectives and features, and other features in accordance with a first embodiment of the present invention, there is provided a method of fabricating a capacitor storage node. The method includes providing a semiconductor substrate. A lower insulating layer, an etching stopper layer and an upper insulating layer are sequentially formed on the semiconductor substrate. Preferably, the etching stopper layer is made of a silicon nitride and the upper insulating layer is made of a silicon oxide. The stacked layers are patterned to form a storage opening to a predetermined portion of the semiconductor substrate. A first conductive layer and a second conductive layer as for a storage node are formed on the upper insulating layer, following the topology of the storage opening therein. The first conductive layer is formed by the process of depositing an amorphous silicon, and annealing the amorphous silicon to crystallize it, to form polysilicon which suppresses growth of HSG silicon thereon. Alternatively, the first conductive layer can be directly made of polysilicon. Namely, polysilicon can be directly formed on the upper insulating layer as the first conductive layer.
The second conductive layer is formed by depositing amorphous silicon. The second and first conductive layers on the upper insulating layer are patterned to be left only in the storage opening, to form a storage node. The second conductive layer defines an inner wall of the storage node, and the first conductive layer defines an outer wall of the storage node that is in contact with (i.e., is surrounded by) the upper insulating layer. Using the etching stopper layer, the upper insulating layer is removed to expose the first conductive layer, i.e., the outer wall of the storage node. An HSG silicon forming process is carried out on the exposed inner and outer walls of the storage node. However, HSG silicon is grown only to a predetermined size on the inner wall of the storage node made of amorphous silicon. Since the outer wall of the storage node is made of crystallized silicon (polysilicon), HSG silicon can not be grown thereon. Accordingly, there are substantially no electrical bridges between adjacent storage nodes.
More particularly, forming the storage opening comprises patterning the upper insulating layer until the etching stopper layer is exposed, to form a storage node opening, and etching the exposed etching stopper layer and the lower insulating layer until the predetermined portion of the substrate is exposed, to form a storage contact opening that is aligned to the storage node opening. Preferably, the upper insulating layer is further selectively etched with respect to the etching stopper layer, to enlarge the dimension of the storage node opening, after forming the storage node opening.
Forming of the lower insulating layer comprises forming a first insulating layer over the semiconductor substrate, forming a bit line with a capping layer on the first insulating layer, forming a second insulating layer on the first insulating layer and on the bit line with the capping layer, forming a third insulating layer on the second insulating layer to prevent oxidation of the bit line, and forming a fourth insulating layer on the third insulating layer. Preferably the bit line capping layer has an etching selectivity with respect to the first and second insulating layers. The third insulating layer has an etching selectivity with respect to the second and fourth insulating layer and the etching stopper layer has an etching selectivity with respect to the fourth insulating layer. Preferably, the fourth insulating layer is made of silicon oxide, the third insulating layer is made of silicon nitride, the second and first insulating layers are made of silicon oxide and the bit line capping layer is made of silicon nitride. Etching the lower insulating layer for the formation of the storage node contact opening comprises etching the fourth insulating layer with an etching recipe that selectively etches silicon oxide with respect to the silicon nitride third insulating layer, etching the third insulating layer with an etching recipe that selectively etches silicon nitride with respect to the silicon oxide second insulating layer, and etching the second and first insulating layers with an etching recipe that selectively etches silicon oxide with respect to the silicon nitride bit line capping layer. The storage node contact opening is self-aligned to the storage node opening, and is formed between the bit line and an adjacent bit line, to expose the predetermined portion of the substrate.
Providing the semiconductor substrate comprises forming a transistor on the semiconductor substrate, forming an insulator on the transistor and on the semiconductor substrate, patterning the insulator to form a storage contact pad opening and a bit line contact pad opening away from the transistor, filling the storage contact pad opening and bit line contact pad opening with a conductive material, and planarizing the conductive material until the insulator is exposed, to form a storage contact pad and a bit line contact pad. The bit line is formed to be in electrical contact with the bit line contact pad, and the storage opening is formed to expose the storage contact pad.
Selective etching of the second and first conductive layers on the upper insulating layer, so as to be left only in the storage opening to thus form a storage node, comprises forming a planarizing insulating layer on the second conductive layer to fill the storage opening, etching the planarizing insulating layer, the second conductive layer and the first conductive layer until the upper insulating layer is exposed, and removing the remainder of the planarizing insulating layer in the storage opening, to expose the second conductive layer.
To achieve these objectives and features, and other features in accordance with a second embodiment of the present invention, there is provided a method of fabricating a capacitor storage node in a semiconductor device. The method includes forming a transistor on a semiconductor substrate. An insulator is formed on the substrate and on the transistor. A bit line contact pad and a storage contact pad are formed in the insulator away from the transistor, to be electrically connected to the semiconductor substrate. A first insulating layer is formed on the semiconductor substrate and on the contact pads. A bit line is formed on the first insulating layer to be electrically connected to the bit line contact pad through the first insulating layer. The bit line is made of a bit line conductive layer with a capping layer thereon and a side wall spacer. A second insulating layer is formed on the first insulating layer and on the bit line. A third insulating layer is formed on the second insulating layer to prevent the oxidation of the bit line. A fourth insulating layer is formed on the third insulating layer. An etching stopper layer is formed on the fourth insulating layer. A fifth sacrificial insulating layer is formed on the etching stopper layer. The stacked layers are patterned to form a storage opening which exposes the storage contact pad. A first conductive layer and a second conductive layer for a storage node are formed on the fifth sacrificial insulating layer and in the storage opening. The first conductive layer is made of a material that can prevent growth of HSG silicon on the surface thereof. As an example, polysilicon can be used. The polysilicon can be formed by a process of depositing amorphous silicon, and then annealing the amorphous silicon to crystallize it. Alternatively, the polysilicon can be directly deposited at a predetermined temperature.
The second conductive layer is made of a material layer that allows growth of HSG silicon on the surface thereof. As an example, amorphous silicon can be used. A sixth insulating layer is formed on the second conductive layer to fill the storage opening. The sixth insulating layer, and the second and first conductive layers, are etched until the fifth sacrificial insulating layer is exposed, to form a storage node. The remainder of the sixth insulating layer in the storage opening and the fifth sacrificial insulating layer outside of the storage node are removed, to expose an inner wall and an outer wall of the storage node. The second conductive layer defines the inner wall and the first insulating layer defines the outer wall. HSG silicon is formed on the inner wall.
More particularly, the first, second, fourth, fifth and sixth insulating layers respectively comprise an oxide; and the etching stopper layer, the third insulating layer, the bit line capping layer and the side wall spacer respectively comprise a silicon nitride.
Forming the storage opening comprises patterning the fifth sacrificial insulating layer until the etching stopper layer is exposed, to form a first opening for a storage node, and patterning the etching stopper layer and the fourth, third, second and first insulating layers, to form a second opening for a storage contact which exposes the storage contact pad. Preferably, the fifth sacrificial insulating layer is further selectively etched with respect to the etching stopper layer, to enlarge the first opening, after forming the first opening.
To achieve these objectives and features, and other features in accordance with a third embodiment of the present invention, there is provided a method of fabricating a capacitor storage node in a semiconductor device. The method includes forming a transistor on a semiconductor substrate. An insulator is formed on the substrate and on the transistor. A bit line contact pad and a storage contact pad are formed in the insulator away from the transistor, to be electrically connected to the substrate. A first insulating layer is formed to insulate the pads and transistor. A bit line is formed on the first insulating layer to be electrically connected to the bit line contact pad through the first insulating layer. The bit line is made of a bit line conductive layer with a capping layer thereon and a side wall spacer. A second insulating layer is formed on the first insulating layer and on the bit line. A storage contact plug is formed in the second and first insulating layers to be in electrical contact with the storage contact pad. An etching stopper layer and a sacrificial insulating layer are sequentially formed on the second insulating layer and the storage contact plug. The sacrificial insulating layer and the etching stopper layer are patterned to form a storage node opening. A first conductive layer and a second conductive layer for a storage node are formed on the sacrificial insulating layer and in the storage opening. The first conductive layer is made of a material layer that can prevent growth of HSG silicon on the surface thereof. As an example, polysilicon can be used. The polysilicon can be formed by the process of depositing amorphous silicon, and then annealing the amorphous silicon to crystallize it. Alternatively, the polysilicon can be directly deposited at a predetermined temperature.
The second conductive layer is made of a material layer that allows growth of HSG silicon on the surface thereof. As an example, amorphous silicon can be used. A planarization insulating layer is formed on the second conductive layer to fill the storage opening. The planarization insulating layer, and the second and first conductive layers, are etched until the sacrificial insulating layer is exposed, to form a storage node. The remainder of the planarization insulating layer in the storage opening and the sacrificial insulating layer are removed, to expose an inner surface and an outer surface of the storage node. The second conductive layer defines the inner surface and the first conductive layer defines the outer surface. HSG silicon is formed on the inner surface.
Forming the storage node opening comprises patterning the sacrificial insulating layer until the etching stopper layer is exposed, selectively etching the sacrificial insulating layer with respect to the etching stopper layer, to enlarge the dimension of the opening, and patterning the exposed etching stopper layer until the storage contact plug is exposed.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.